The continuing push to produce faster semiconductor devices with lower power consumption has resulted in device miniaturization. In particular, smaller channel lengths are conducive to the low voltage and faster operation of semiconductor devices, such as complementary metal oxide (CMOS) transistors. With shrinking process geometries, the use of new materials is being explored to further reduce power consumption and increase switching speeds.
Currently, there is interest in improving carrier mobility by inducing stress in the channel region of semiconductor substrates. In some cases, a portion of the substrate is removed and replaced with a material that can serve as source or drain structures and, also provide a tensile or compressive stress to the channel region. Unfortunately, some of these devices can have an undesirably high leakage current, and in some cases, a high diode leakage. Additionally, the process used to remove portions of the substrate can introduce non-uniformities into the substrate surface, making it more difficult to form contacts to the device. Furthermore, such devices, when comprising nickel silicide source or drain electrodes, are prone to forming pipe-shaped defects that can short-out the device or otherwise cause a device malfunction.
Accordingly, what is needed is a semiconductor device and its method of manufacture that imparts strain into the channel region of the device while not suffering the drawbacks of prior art devices.